Semiconductor processing often involves the formation of metallic interconnect lines, which are typically etched from a metal containing layer disposed above a substrate, and which are then employed to couple various devices on the substrate together to form a desired circuit. Metallic interconnect lines are often formed from a metal layer deposited on a semiconductor substrate as part of a larger stack of materials which may include barrier layers and/or anti-reflective coatings.
When a relatively tall stack of metal is to be etched for the purpose of defining a metal interconnect pattern or the like, it is sometimes desirable to use an oxide-based hard mask in place of, or in addition to an organic photoresist layer for controlling the etch-base patterning of the metal stack. The hard mask is typically used when it is possible that the photoresist layer may not be sufficiently strong enough alone to withstand the erosive environment of a harsh and/or long metal etching process.
When a hard mask layer is used for propagating an etch pattern from a photoresist pattern to an underlying metal layer, the organic photoresist layer is often first provided above the still blank (i.e., unpatterned) hard mask layer. The organic photoresist layer is then exposed to appropriate radiation and the exposed photoresist layer is then developed to leave behind the polymerized organic photoresist material over the blank hard mask layer. An oxide etching process is then typically used to pattern through the relatively thin hard mask layer using the pre-patterned photoresist layer as a pattern-proliferating mask. These steps are carried out before metal etching through the underlying metal layer is undertaken. In other words, the lithographic pattern that is provided by the photoresist layer is copied into the more durable hard mask layer and the hard mask layer pattern is then used to etch the pattern into the underlying metal interconnect layer. A variety of different materials have been proposed as hard mask layers, including various oxides.
Unfortunately, it is often the case that a significant amount of micromasking residue can be left behind on an underlying barrier layer, such as titanium-containing anti-reflective coatings, and that this micromasking residue may interfere with proper etching of the underlying metal layer. More specifically, the micromasking residue may create undesirable short circuits between metal interconnect lines in the semiconductor device.
Various proposals have been made for alleviating the problem of micromasking residues. For example, various washing methods have been proposed to be carried out between the etching of the hard mask material and the etching of the underlying barrier layer and/or metal interconnect layer. Additionally, the deposition of additional oxygen-deficient layers between hard mask materials and barrier layer materials has also been proposed. However, the reduction of micromasking residue is not always sufficient and the addition of washing steps and/or steps to remove the residue can decrease efficiency and/or increase the cost of the semiconductor processing.
Therefore, there is a need in the art for an improved method of etching metal stacks such that the amount of micromasking residue is reduced.